资源列表
ch1
- cpld/fpga概述以及硬件描述语言设计的一些概念-cpld/fpga outlined as well as the hardware descr iption language design some of the concepts
Key-200893142940130
- 关于地铁售票的一些功能 基于自动买票的VHDL设计程序 比较经典-Subway ticket on some of the features of the VHDL-based auto-buying classic design procedure
usb_jtag
- FPGA、CPLD芯片的usb数据下载线，下载速度是并口的5位，内有原理图用程序-FPGA, CPLD chip usb data download lines, download speed is the parallel port of the five, with a schematic diagram of procedures in
I2C
- I2C的VHDL源码，从机模式，编译通过。-I2C the VHDL source code, from the mode, the compiler through.
an_jian_qu_dou_dong
- 可以用于按键去抖动的电路应用，采用vhdl编写-Button can be used to jitter circuit applications, the preparation of the use of VHDL
alarm_system
- 电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach
i2c_Verilog
- Verilog开发的I2c接口模块，如何需要更详细的资料，请参考www.opencores.org网站-Verilog development I2C interface module, how the need for more detailed information, please refer to website www.opencores.org
Verilog_Example
- 设计与验证Verilog_实例，经典的HDl书籍，强烈推荐-Design and verification Verilog_ examples Hdl classic books, strongly recommend
vhdl
- vhdl语言例程集锦.pdf，全部的例子，看你会不会偷了-VHDL language routines Collection. pdf, all the examples, you will not see stealing
38d7dd72-eb79-40e9-b362-77110e0ab3b9
- 基于EDA的八音自动播放电子琴设计 内有VHDL语言设计 有-The octave-based EDA player automatically have a flower design language VHDL design
VHDL_MIAOBIAO_CODE
- 基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码-CYCLONE series based on the FPGA EP1C3T144C8 stopwatch VHDL code
jianfaqi
- 用硬件描述语言编程实现减法器,实现两个操作数的减法-Using hardware descr iption language programming subtraction, and the achievement of the two operands of the subtraction