资源列表
bits
- verilog语言，移位寄存器实现的序列检测器-verilog language, to achieve the shift register sequence detector
fsm
- verilog语言，有限状态机实现的序列检测器-verilog language, finite state machine sequence detector
counter
- Verilog语言编写的8进制同步、异步加法计数器-Verilog language octal synchronous, asynchronous addition counter
ALU
- Verilog编写的ALU，可实现数学、移位、逻辑运算-ALU Verilog prepared, enabling mathematics, shift, logical operations
22
- VHDL出租车计费器设计论文文档，word格式，内容详细，介绍完整，功能强大。-Taxi meter VHDL design paper documents, word format, detailed descr iption complete and powerful.
11
- VHDL出租车计费器设计，课程设计完美通过优秀,文档内容是该课程设计的论文，里面详细介绍了该设计的实现和各个模块的具体实现细节，这是河南科技大学课程设计内容-Taxi meter VHDL design, curriculum design the perfect through the excellent content of the document is that the curriculum design papers, which detailed the specific imple
11
- VHDL出租车计费器设计，课程设计完美通过优秀,各个功能模块讲解十分清楚-Taxi meter VHDL design, curriculum design the perfect through outstanding
OR1200-Voice
- 基于EP3C开发板的采用OR1200 CPU的语音回放系统-Voice playback system based on OR1200
10_100M-Ethernet-
- 10M 100M 以太网 Verilog 源代码-10M 100M Ethernet
i2c_master
- I2C Controller for Serial EEPROMs
I2C-SourceCode
- I2C Inter Integrated Circuit Master Controller SourceCode
SPI-SourceCode
- SPI Serial Peripheral Interface WISHBONE Controller SourceCode