- chat 这是一个网络聊天程序
- Automatic-Calculation-for-different-function Automatic Calculation for different function (A/B A*B A
- KinectShapeGame 微软Kinect的一个捕捉人体骨骼小游戏源程序
- HeatConductionToolbox 热传导MATLAB工具箱提供了一组为一维热传导计算功能通过为界区间和数值方法分析方法（显性
- iter_iter_size_char Number of (read and write) dependencies that must be resolved before this instruction can be scheduled.
- icuplug API allowing run
资源列表
sdram_demo
- 主要编写了sdram的驱动程序开发程序，在开发板上运行成功-this file is to drive sdr sdram , it runs on platform successfully
modelsim
- 一款用于扩频通信发射系统的CPLD程序，基本的QPSK调制-A used in spread spectrum communication system of CPLD program, basic QPSK modulation
DDSN
- quartus II 13.0 DDS工程文件，采用VHDL编写，可输出正交两路正弦信号。可以直接用modelsim-alter 仿真-quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter
traffic_cntrl
- FSM based traffic light controller
parallel_prefix_flag
- design of parallel prefix adder in verilog
image_ver_main
- The design of multi level sensor is mostly based on FSM controller-The design of multi level sensor is mostly based on FSM controller
des
- des algorithm Simple
FPGA-PWM_LED
- FPGA 实现PWM控制LED的例程 具有参考意义-FPGA to achieve LED PWM control routine
Digital-dynamic-display-FPGA
- 数码管动态显示 FPGA verilog 基本例程-Digital dynamic display FPGA
szz
- 基于CPLD的数字钟，用VHDL语言编写，数码管显示，可调时调分，具有整点报时功能。-CPLD-based digital clock, using VHDL language, the digital display, an adjustable transfer points, the whole point timekeeping function.
sata_phy_latest.tar
- 用verilog写成的sata2的phy物理层，可应用与sata2的控制层下层接口！-Phy written by verilog sata2 the physical layer, the lower layer can be applied to the interface control layer and sata2!
freq
- verilog 编写的频率计 管脚绑定支持Xilinx Spartan6-verilog prepared frequency meter pin binding support Xilinx Spartan6