资源列表
FA
- 使用VERILOG實現全加器的設計,並附上TB供測試-Use VERILOG achieve full adder design, together with a test for TB
VerilogHDL_advanced_digital_design_code_Clock_gene
- VerilogHDL_advanced_digital_design_code_Clock_generator VerilogHDL高级数字设计源码Clock_generator
i2c
- 模拟I2c的源程序，可以用51来控制传输数据-Analog I2c the source can be used to control the transmission of data 51
meter_bucket_renew
- 实现一个简单的令牌桶算法（按照固定速率向桶中放钱。 传送信息包要按照大小花钱买。 钱够了就送出 钱不够就要等候储蓄 ）-Implement a simple token bucket algorithm (Putting the money into the bucket at a fixed rate and pay the price according to the information size which you need to send. The informati
Multiplier4b
- This a code of a multiplier for two 4 bits numbers written in Verilog.-This is a code of a multiplier for two 4 bits numbers written in Verilog.
LCD_TEST
- Hi, This Verilog practice code-Hi, This is Verilog practice code
URAT
- Verilog硬件描述语言，RS232串口发送接收程序-Verilog hardware descr iption language, RS232 serial port send and receive program
project
- It provides the code of or and decoder24 and encoder42 in VHDL language
Verilog16-bit-counter-design
- Verilog16位计数器设计,可实现简单的16位数的计算。-Verilog16 bit counter design, simple 16-digit calculation.
FIRfilterverilogHDL
- FIR滤波器的verilog HDL代码示例，以16阶为例-Verilog HDL code for fir filter
RC17871BSW
- RC7871B控制CPLD程序，用于实现芯片交互性数据传递和相关控制功能-for RC7871B CPLD Vhdl contorl
RC17872BSW
- 用于RC17872BSW芯片控制CPLD，用于复杂逻辑交互控制-for RC17872BSW control CPLD