资源列表
38yimaqiforep8c35
- 38译码器，cyclone2ep2c35,altera公司，-38 decoder, cyclone2ep2c35, altera
WDDRGEN
- Address generation for twiddle factors
PVCell
- mast语言写的太阳电池组件模型，可以任意设置串并联数量，调整光强-mast solar component model written in
NCO-CIC
- 是CIC滤波器的一部分，是积分部分，可以实现3倍抽取。NCO-Is part of the CIC filter is an integral part, can achieve three times the extract.
buzzer_sos
- verilog语言编写的能有次序控制输出莫斯密码SOS的模块。-verilog language written in order to have control of the module output Moss SOS password.
mymima
- 密码锁的VHDL程序-locks VHDL procedures
dac
- 0～5伏可调数字电压源，以5伏为基准电压，数码管显示当前电压值，使用VHDL语言实现，程序都加了注释，方便阅读。 -0 ~ 5 V digital voltage source adjustable to 5 V for the voltage reference, digital tube displays the current voltage value, the use of VHDL language, the program notes are added to facilita
VGA
- 基于FPGA的Verilog语言的VGA测试程序，仅供参考-FPGA-based VGA Verilog language test procedures for reference
MAX Pool Code
- This is the verilog code for max pooling method.
232_receiver
- Rs232 receiver usage
rd_wr_control
- USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
usb_model
- usb接口model原码设计,可以模拟USB的接口数据接收,用于usb接口数据的仿真.-usb interface model of the original codes designed to simulate USB interface data reception, usb interface data for the simulation.