文件名称:DC-Adder_Array
-
所属分类：
- 标签属性：
- 上传时间：2015-07-14
-
文件大小：6.67kb
-
已下载：0次
-
提 供 者：
-
相关连接：无下载说明：别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容来自于网络，使用问题请自行百度
要求采用快速进位链（Look Ahead）设计一个21位加法器；
2) 采用结构化的设计方法，所有加法器均采用步骤1）的21位加法器；
3) 在加法器阵列中加入流水线结构（Pipelinc），输入连续送数，输出连续出结果，流水线填满后每拍输出一个结果；
-1) requires the use of fast carry chain (Look Ahead) design a 21-bit adder
2) the use of structured design methods, all adders are used in step 1) 21-bit adder
3) was added in the adder array pipeline structure (Pipelinc), enter the number of continuous feed, continuous output the results after each shot output lines to fill a result
2) 采用结构化的设计方法，所有加法器均采用步骤1）的21位加法器；
3) 在加法器阵列中加入流水线结构（Pipelinc），输入连续送数，输出连续出结果，流水线填满后每拍输出一个结果；
-1) requires the use of fast carry chain (Look Ahead) design a 21-bit adder
2) the use of structured design methods, all adders are used in step 1) 21-bit adder
3) was added in the adder array pipeline structure (Pipelinc), enter the number of continuous feed, continuous output the results after each shot output lines to fill a result
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DC-Adder_Array/
DC-Adder_Array/Adder_Array.v
DC-Adder_Array/CLA_20.v
DC-Adder_Array/CLA_4.v
DC-Adder_Array/LOG_OP.v
DC-Adder_Array/pipeline_control.v
DC-Adder_Array/pipeline_first.v
DC-Adder_Array/pipeline_fourth.v
DC-Adder_Array/pipeline_second.v
DC-Adder_Array/pipeline_third.v
DC-Adder_Array/transcript
DC-Adder_Array/Adder_Array.v
DC-Adder_Array/CLA_20.v
DC-Adder_Array/CLA_4.v
DC-Adder_Array/LOG_OP.v
DC-Adder_Array/pipeline_control.v
DC-Adder_Array/pipeline_first.v
DC-Adder_Array/pipeline_fourth.v
DC-Adder_Array/pipeline_second.v
DC-Adder_Array/pipeline_third.v
DC-Adder_Array/transcript
1999-2046 搜珍网 All Rights Reserved.
本站作为网络服务提供者，仅为网络服务对象提供信息存储空间，仅对用户上载内容的表现方式做保护处理，对上载内容本身不做任何修改或编辑。