资源列表
DE2_70_LTM
- VERILOG语言环境的LTM显示开发封装模块。-VERILOG language environment of the LTM display development encapsulated module.
09081113
- 简单计数器，分频器，全加器等vhdl程序等-Simple counter, divider, adder vhdl procedures such as
BR262降噪芯片寄存器设置
- 针对BR262器件的寄存器控制，可设置增益大小，数字接口，模拟接口输出等功能
vhdl_handbook
- VHDL编程手册包括VHDL常用的实例-vhdl programming handbook
led_0000_9999
- 基于FPGA，VHDL语言的数码管电子钟-Based on FPGA, VHDL language of digital tube electric clock
VHDl-Jiaocheng
- 讲述VHDL语言的不错的入门书籍，是比较经典的一本书，大家可以下来学习-Good about the VHDL language entry books
canlender_clock
- 电子日历的设计源代码 verilog程序设计 通过仿真-The design of electronic calendar program design verilog source code simulation
spramipcore
- 使用vhdl语言在fpga环境下实现ip core spram-Environment in fpga vhdl language used to achieve ip core spram
value_to_ascii
- 使用Verilog HDL 进行数值与字符ASCII码的转化，实现串口正确显示字符，编程环境Quartus -Use Verilog HDL to numerically with ASCII characters transformation, realize serial display character correctly, Quartus ii programming environment
data-Acquisition-by-PCI-
- 基于FPGA的PCI数据采集程序。PCI9054时序控制,开发语言verilog,开发环境quartus-FPGA-based PCI data acquisition program
gen_fifo_usb1
- slaver fifo测试模块，分为三个模块，generate产生数据，然后写如fifo.再传如usbslaver fifo-slaver fifo test module consists of three modules, generate production data, and then write as fifo. re-transmission, such as usbslaver fifo
Quartus
- 仿真软件开发应用，法家来试试，学学，不错-QUARTUS