资源列表
PCIE_DMA_DDR3_verilog_design
- 基于xilinx fpga的pci-e到dma再到ddr3的数据传输完整设计-PCIE_DMA_DDR3 verilog reference design
121114156PCIE_DMA_DDR3_verilog_design
- 基于FPGA的pcie dma设计，可参考应用。(FPGA based PCIe DMA design, you can refer to the application.)
111
- 一个完整的SDRAM调试程序，在QuartusII下运行，保证可用。-A complete SDRAM debugger, run in QuartusII ensure available.
I.MX51datasheet.pdf.tar
- facecale i.MX515 datasheet
median_filter
- 中值滤波的verilog实现，完整工程，调试通过-Median filter verilog achieve complete engineering, debugging through
FPGA-_RS232
- 在完成了系统逻辑的设计和功能仿真后，我们要对所生成的VHDL文件进行综合，生成门级网表文件，-afew fwefwf 34rf4f
FPGA-design-note
- 参加fpga培训班的讲义 自己做的笔记，适合fpga高级设计人员。-Participate in the lecture course fpga own notes, senior designer for fpga.
Matlab-m-sequence-generator
- 介绍m序列和教你如何利用matlab进行编译m序列-Introduction of m-sequences and teach you how to use the matlab compiled m-sequence
counter8
- 使用vhdl语言和quartus平台建立的8位计数器的简单仿真-Using vhdl language and platform quartus established 8-bit counter simple simulation
iic
- 通过verilog语言实现了关于IIC协议，并且通过了modelsim的功能仿真验证以及板卡之间的RTL调试。-the verilog code about IIC standard，checked by modelsim，and make ture the IIC function in RTL。
lab4_project
- lab4中基于ISE的lab4实验的程序源代码，这里使用的是ISE13.4的版本-lab4 in ISE-based lab4 experimental program source code, here is the version ISE13.4
all_test_2c5
- 买的开发板上自带的例程，上传与电子爱好的共享-To buy the development of on-board built-in routines, upload and e-loving sharing