资源列表
mul
- 八位乘法器的VHDL程序，按照乘法的运算规则利用分支语句判断所有情况，最后累加求的结果-8 multiplier VHDL programs, in accordance with rules of multiplication operations to determine all the circumstances of the use of a branch statement, the final cumulative result of demand
50M
- verilog 语言写的分频模块，实现用50Mhz的时钟频率分出1hz的频率，也就是一秒的频率-verilog language sub-frequency module, using the 50Mhz clock frequency 1hz separation, that is, the frequency of second
traffic-light
- 基于VHDL语言开发实现交通灯的功能,实现倒计时，直行，向左转向右走的功能控制-traffic light design
ahb_ram
- AHB接口的ram控制器，可靠性非常强。除了两个周期内发生读到写或写到读的极限情况（一般处理器设计中不会有这种传输方式），其他传输方式完全没有问题-AHB interface ram controller, reliability is very strong. In addition to occurring in two cycles read or write read write the limit (usually processor design will not have such
calculator
- VHDL编写计算器，功能包括：加，减，乘，除。通过keypad输入及输出-Calculator written with VHDL
lcd_test
- Xilinx Spartan-3E实验板上基于verilog控制lcd屏幕A到Z反复轮转显示。-Xilinx Spartan-3E verilog based test control board lcd screen A to Z repeated rotary display.
SPI_MISO
- SPI-MOSI程序,奇主机输出，从机输入-SPI
median-filter
- 基于FPGA的图像中值滤波算法的优化及实现vhdl-中值滤波 利用VHDL语言实现三级流水线中值滤波-FPGA-based image filtering algorithm optimization and realization of vhdl-median filter using VHDL language three pipelined median filter
MEDIAN.v
- fpga 的 median的verilog实现-median of verilog implementation
microblaze-elf-tools-20060213.tar
- FPGA 上的嵌入式系统设计实例，SPARTEN-3E-FPGA, embedded system design example, SPARTEN-3E
PWM
- LPC1768 PWM脉宽调制，源码。-LPC1768 PWM pulse width modulation , the source code.
tPad_Picture_Viewer
- tPad DE2-115/70可用的图片浏览设计程序，原装程序，可下载到带触摸板的DE2开发板上调试，代码可修改-tPad DE2-115/70 picture browsing design program available, the original program, with a touch pad can be downloaded to the DE2 board debugging, code can be modified