资源列表
hidejj
- 实现线性反馈移位寄存器的verilog实现(lfsr use verilog for the zip)
CPLD
- 数字频率计在FPGAEP4CE10F17C8上的功能实现和运用(Application of digital cymometer in FPGA)
CPLD
- CPLD的介绍，请认真看，很基础，可以打印出来(CPLD introduction, please look carefully, very basic, you can print out)
FIFO Design Using Verlilog
- DFF with fifo concepts
FIFO Details
- FIFO Design PDF files
m-test
- 产生小m序列，用于扩频系统中，仿真测试正确，反馈级数为4(Generating m sequences)
Altera FPGA_CPLD设计_高级篇【www.ourfpga.com】
- Altera FPGA_CPLD设计_高级篇,对fpga的提高很有帮助(can improve the application of fpga)
BMD_design_gen2_x4_with_Chipscope
- PCIE BDM官方实例，xapp1052(PCIE BDM XAPP1052 FROM XILINX)
frequency
- 基于Verilog HDL数字频率计的设计与实现(Design of Verilog HDL Digital Frequency Meter)
实验4 串口实验
- TM32F4 通过串口和上位 机的对话， STM32F4 在收到上位机发过来的字符串后，原原本本的返回给上位机(Tm32f4 through the serial port and PC dialogue, stm32f4 in the host computer sends the received string, exactly back to the host computer)
en.SPI_EEPROM_Verilog_models_V10
- spi接口的eeprom模型，型号为st公司m65pxx(The eeprom model of spi interface is st company m65pxx)
manual
- MACHXL Software User's Guide 1993 Advanced Micro Devices, Inc.