资源列表
VerilogHDL硬件描述语言
- Verilog语言入门教程，详细讲述了Verilog语法和应用(Verilog language introductory course, detailing the Verilog syntax and Application)
cnt
- 在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表-In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch
ethernet_tri_mode
- 三速以太网接口模块verilog源码和测试-Triple-speed Ethernet interface module verilog source code and test
ise11tut
- Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use inthe development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, downlo
FPGA-FIR
- 基于Xilinx FPGA实现的系数可装载数字滤波器源代码
fft(VHDL)
- 该源码是fft的VHDL实现，通过FPGA下载验证通过-The source is the fft of the VHDL implementation, through verification by FPGA download
Xilinx-FIR
- 基于Xilinx FPGA实现的系数可装载数字滤波器源代码-Configurable Digital Filter Based on FPGA (using Verilog under Matlab 2008a)
intro_to_quartus2_chinese
- 介绍quartus IＩ 汉语教程，非常难得，-A Chinese introduction to quartus II.
quartus2
- quartus2的中文文档，不是很全，仅供大家学习-quartus2 the Chinese document, not very wide, only for them to learn
Picture_Downloader
- Picture downloader IP using Quartus II via JTAG
IEEE_standar
- IEEE标准VHDL的一些规范说明，介绍如何利用VHDL进行设计-IEEE standard VHDL some of the standard descr iption of how to use VHDL to design
cafe_you_wanna
- 一款咖啡机代码，收5角1元，3元一杯，用verilog编写-cafe code