资源列表
PROCESS_CLARA_4
- 引用了TXT文档数据导入激励数据源的方法-TXT document referenced data into the data sources for excitation
Flash_8816_2_32
- tools for your o2 xda atom
YIWEIJICUNQI
- 两种移位寄存器的设计，分别为通用移位寄存器跟桶形移位寄存器-Two kinds of shift register design, namely, universal shift register with the barrel shifter
timer
- 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
SSRAM_CONTROLLER
- sram controller design for GSI sram working
1
- 将“How are you”通过LCD显示出来，并能够在you前面换行-display how are you on the LCD
Traffic-light
- 基于vhdl语言的交通信号灯控制程序，使用软件为Quartus II，硬件为FPGA。-Traffic lights control procedures
uart_rx
- 基于verilog的uart接收模块，16倍波特率采样，具有可选择奇偶校验功能，仿真成功。-Based verilog the uart receiver module, sampling 16 times the baud rate, parity function with selectable, successful simulation.
fcsr
- 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
ALU
- 在Xilinx7.1平台下编写的ALU代码，可以实现五位加法、减法、与、异或四种运算！-Xilinx7.1 platform in the preparation of the ALU code, can be achieved five adder, subtraction, and, four computing XOR!
ss
- 智能车寻迹（PWM调速）和行驶时间显示，VHDL语言编写-Smart car tracing (PWM speed) and travel time
divider
- 用verilog实现一个被除数位8位、除数为4位的高效除法器-Verilog to achieve a dividend of 8, division by four efficient divider