资源列表
no
- My verilog codes.l vdkvmomvemcmemekmkem
rilog code
- These are my verilog code.
Memory-to-store-data
- Memory to store variable amount of data
scr
- 这是一个用verilog编写的基于IIC接口的控制eeprom的程序代码。程序经过验证是正确的。对不了解IIC的人来说是很好的资料。-This is based on the control eeprom IIC interface program code written in a use verilog. Program proven to be correct. IIC do not understand people who are very good information.
MAX10-on-chip-flash-controller
- Altera MAX10 FPGA on-chip flash控制器代码，虽然由QII生成，但可以从中学习到很多硬件描述语言的设计方法，希望能够帮助那些正在学习VHDL语言设计的人。-Altera MAX10 FPGA on-chip flash controller code, although generated by QII, but you can learn a lot of hardware descr iption language design methods, hoping t
qam16-TX
- 基于Altera MAX10 FPGA的QAM16发送端设计代码，其中采用了MAX10 Fir滤波器IP核。供相关设计人员参考，或者进一步咨询本人。-Based on Altera MAX10 FPGA design of QAM16 the sender code, which uses the MAX10 Fir filter IP core. Related reference for designers, or further consultation himself.
crc32
- 基于Verilog语言描述的CRC32生成和校验电路。连续或间断地4位并行数据输入，实时产生CRC32结果。-CRC32 generation and checking circuits based on Verilog language descr iption. Continuously or intermittently four parallel data input, real-time produce CRC32 result.
i2c_master_controller
- Verilig语言描述的I2C Mater控制器的IP核，已经过实践应用，适合于FPGA I2C接口设计应用。本IP核在Altera QII 15.1软件环境下综合，并且包含基于NiosII Gen2处理器的i2c软件驱动代码。-Verilig language I2C Mater described controller IP core, has been the practical application, suitable for FPGA I2C interface design app
Fast Vector Multiplication
- Fast Vector Multiplication in VHDL with carry save adders and final ripple carry adder
niyiming
- 矩阵键盘扫描以及数码管自动加一计数显示，适合初学者参考-Matrix keyboard scanning and automatically add a digital counter display, suitable for beginners reference
8bit-cpu
- VHDL由简单存储器，计数器等搭建最终实现8位的cpu设计-VHDL realization 8 of cpu design
multiplier-ROM--FIFO-memory
- 布斯，阵列乘法器，加减交替除法器，以及ROM存储器，FIFO存储器-Booth, array multiplier, divider alternately add and subtract, and ROM memory, FIFO memory