资源列表
DDS
- 基于FPGA完成2001年电子设计竞赛直接数字频率合成器，有FPGA部分、MSP430程序以及相互通信的程序，完成题目全部要求-FPGA-based Electronic Design Competition 2001 complete direct digital frequency synthesizer, there is part of the program FPGA, MSP430 procedures and communicate with each other, to comp
divider7_50
- 一个关于占空比为50 的七分频器，是各个公司面试经常考试的题目-A 50 duty on seven dividers, each company for an interview is often the subject of examination
pwm
- 一个宽度脉冲调制pwm的模板，因为是学习使用的，增加了数据输入以便在开发板的led灯中观看实验现象，输入数据越大led的亮度越大-A pulse width modulation pwm template, because it is learning to use, increasing the data input for viewing experimental phenomena in the development board led lamp, the greater the gre
VHDL-Gray-code
- 基于vhdl格雷码设计代码，调试过没错误。-Gray code design based on VHDL code, debugging didn t mistake.
tst_bench_top
- I2C控制总线的测试平台testbench，用于验证I2C主机冲击交互的正确性-I2C control bus test platform testbench, used to verify the correctness of the interaction I2C master impact
i2c_slave_model
- I2C控制总线的重机模型，用于验证I2C设计是否实现了功能描述-I2C bus control heavy machine model, used to verify whether the design implements I2C Functional Descr iption
i2c_master_byte_ctrl
- I2C控制总线按照word写，用verilog实现的主机写功能-I2C control bus according to the word write and write functions implemented by host verilog
i2c_master_bit_ctrl
- I2C控制总线主机，按照字节写设计的verilog代码，由于选项中没有verilog这项，因此选择VHDL-I2C control bus master, according to the byte write verilog code design, because the option is not verilog this, so choose VHDL
i2c_master_top
- I2C控制总线的顶层描述verilog代码，选项中没有verilog语言，故选择VHDL-The function descr iption of I2C bus top level
LED
- LED等循环点亮，verilog实现功能-LED lights light cycle, verilog to achieve functional
ps2
- ps2键盘扫描程序verilog实现，将按键值转化为扫描值-ps2 keyboard scanner verilog realization, the key will be converted to scan values
xilinx-tcl
- Xilinx脚本约束手册，从官方直接拿到的，对Xilinx FPGA开发很有用的。-Xilinx tcl handbook, directly got Xilinx。