资源列表
4bit-adder
- 4 FIT ADDER FULL EXAMPLE IN VHDL LANGUAGE
polynominal-multiplier
- verilog code for polynominal multiplier
code
- verilog code for intrusion matching
2nd-wrk-(1)
- verilog code for shifting of multiplier
1st-wrk
- multiplier code using verilog
eth
- 基于verilog语言的以太网接口的fpga实现，用在无线通信领域，供参考-The Ethernet interface based on verilog language fpga implementation, used in the field of wireless communications, for your reference
pro_1588
- 基于verilog的1588V2协议的fpga实现，目前项目通用代码，供大家参考-Based on verilog 1588 v2 fpga implementation of the agreement, the project general code, for your reference
fft_ifft
- fft and ifft code in verilog
code
- high pass filter and low pass filter
SRIO-phy-code
- SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考-SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development
cpri
- 基于verilog的cpri接口代码，支持各种速率自由切换，量产产品实际应用代码-Cpri interface based on verilog code, support various rate free switch, production products the actual application code
CoreUartTest
- Actel FPGA UART 串口通信模块，调用Actel CoreUART IP核实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-Actel FPGA UART serial communication module, call Actel CoreUART IP core implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.