- MusicPlayerV2.0 能够实现音乐播放和音乐控制音量控制等基本功能
- Resource_Manager_Help_by_Pimen__1.9_ Resource Manager Help by Pimen
- PUguji 详细说明了谱估计的一些原理
- flatber BER performance in flat fading channels using bpsk modulation
- vhdl_code_for_pseudo_random_sequence_generator_in THIS FOR PSEUDO RANDOM SEQUENCE GENERATION DEETAIL
- source-code-of-calculator 一个简易计算器的源码程序
资源列表
altera-TimeQuest_User_Guide
- alter时序约束的开发者手册，从官方直接拿到的。-altera timing handbook，directly got xilinx.
Read_SPI_ADC
- This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.-This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 AD
fnd-clk
- FND, SEGment verilog code
UART_TEST
- this is FPGA Verilog project
LED_FND_LCD
- Hi, This Verilog practice code-Hi, This is Verilog practice code
UART_LED_FND_LCD
- Hi, This Verilog practice code-Hi, This is Verilog practice code
LCD_TEST
- Hi, This Verilog practice code-Hi, This is Verilog practice code
FND_TEST
- Hi, This Verilog practice code-Hi, This is Verilog practice code
UART_PRA
- Hi, This Verilog practice code-Hi, This is Verilog practice code
can
- CAN总线控制器的FPGA源代码，verilog语言编写，支持CAN2.0B协议。对CAN总线开发者非常有用。-FPGA CAN bus controller source code, verilog language, support CAN2.0 protocol B. Developers of CAN bus is very useful.
sine
- FPGA实现正弦波信号的产生，verilog语言-FPGA realization generate sine wave signal, verilog language
DA_TLC5615
- 用FPGA控制DA芯片TLC5615实现数模转换，verilog语言-DA control with FPGA chip TLC5615 to achieve digital to analog conversion, verilog language