资源列表
Dchufaqi
- VHDL实现D触发器包括上升沿触发，下降沿触发，时钟触发-VHDL realize D flip-flop including rising along the trigger, falling edge trigger, triggered the clock
meexternalletterforcsvtu
- ! E:\jogeshwer.zip: Cannot open E:\jogeshwer\RR4_mult_paper.docx The process cannot access the file because it is being used by another process. -! E:\jogeshwer.zip: Cannot open E:\jogeshwer\RR4_mult_paper.docx The process cannot access
New-Compressed-(zipped)-Folder-(5)
- traffic light controller verilog code modelsim tested
New-Compressed-(zipped)-Folder-(4)
- verilog code for sequence detection implemented on FPGA using quartus simulator
bldc_motor_control_design_example
- 无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA- actel VERILOG BLDC control of the use of actel FPGA
siga
- 2014电子设计大赛e题固件模块代码，很好的实现功能。-2014 electronic design contest e Title firmware module code, very good to achieve function.
I2Creadorwrite
- 基于MAX II 系列 epm1270t iic的读写-Based on the MAX II family literacy epm1270t iic
sample-vhdl
- basic vhdl codes for beginers
modelsim-C_compiler_issue
- modelsim的C compiler问题，请需要者下载参考-modelsim the C compiler problem, for those who need to download reference
AD_SAMPLE_PHASE_MATLAB
- 测试多通道AD同步采集信号的相位差,经过实际项目验证-test multi-channel AD sample signal s phase
自定义PWM IP核，符合avalon总线
- 适合初学qsys、nios者，含tb文件，仿真通过，无bug
dds_clk
- VHDL代码实现FPGA中DDS功能，输出频率可调-VHDL code for the FPGA DDS function, the output frequency is adjustable