资源列表
function_generator
- 采用VHDL语言写了一个函数发生器的程序。内含有各个模块，供大家参考，请多批评！-VHDL language used to write a function generator procedures. Contains various modules, for your reference, please criticize!
sram64kx8
- 基于VHDL的一种SRAM模块，简单，但是可参考性强-A VHDL-based SRAM modules, simple, but can be refered strongly
CCMU
- 代码是一个复数乘法器，两个复数相乘，只用到了2个实数相乘，运算量少-Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less
sin_rom(4wzh)
- 基于Quartus II 的信号发生器，通过定制LPM_ROM元件产生正弦波、方波、锯齿波、三角波，分频模块、频率控制模块、按键控制换波形、按键防抖-Quartus II-based signal generator generated by custom LPM_ROM component sine, square, sawtooth, triangle wave frequency module, frequency control module, button control for wa
cmultip
- 用VERILOG HDL 实现节省乘法器的16位复数乘法器-With VERILOG HDL achieve savings of 16-bit complex multiplier multiplier
esign_3c120_v110_qsys_revA
- 基于Altera Qsys vip_example_design_3c120_v110_qsys_revA-Based on Altera Qsys vip_example_design_3c120_v110_qsys_revA
ketflink_fsm
- VERILOG的按键去抖，采用状态机的实现方法-VERILOG shaking the keys to using a state machine implementation
MSP430JIAdds
- MSP430和FPGA通信模块四个ROM,里面包含DDS程序代码，通信代码-MSP430 and FPGA communication module of four ROM, which contains the DDS code
ITU656_chinese
- ITU656的一个介绍。是YUV 4：2：2的！-ITU656 an introduction. YUV 4:2:2 is the!
altera_fifo
- altera 公司的 FIFO 文档，这是设计同步或异步FIFO的重要文档-altera s FIFO document
EDA-test-3
- 大学EDA实验的一些代码 都可以完美运行-University of EDA test some of the code works perfect
cache
- 缓存器 cache verilog 欢迎下载偶-cache verilog