资源列表
flowingled_top
- 8位流水灯，1个LED灯左右来回循环。2个LED灯左右来回循环-About eight water lights, an LED light back and forth cycle. Cycle back and forth about 2 LED lights
LED-R-G-B-main
- LED R G B三色混合调光PWM控制-LED R G B main
lapsa
- 这是清华大学电子系的一个课程作业，要求学生用VHDL实现LAPSA协议。-This is the Department of Electronics, Tsinghua University, one course of operation, require students to achieve LAPSA agreement with VHDL.
LAPS
- 自己实现的一个简单LAPS协议处理器,VHDL语言实现-Their implementation with a simple LAPS protocol handler
Viterbi
- 实现VHDL的维特比译码 -VHDL Viterbi decoding to achieveVHDL Viterbi decoding to achieve
counter
- 用Verilog HDL语言实现FPGA的频率等精度测量。（已经过验证）-Using Verilog HDL language, such as FPGA frequency measurement accuracy. (Has already been verified)
fir
- 利用FPGA中verlog HDL实现FIR滤波功能,可自行设置相关参数，生成模块-Verlog HDL in the use of FPGA realization of FIR filtering, the provision of the relevant parameters can generate module
wave
- 可控脉冲发生器的VHDL源代码。设计文件加载到目标器件后，按下按键开关模块的S8按键，在输出观测模块通过示波器可能观测到一个频率约为1KHZ、占空比为50 的矩形波。按下S1键或者S2键，这个矩形波的频率会发生相应的增加或者减少。按下S3键或者S4键，这个矩形波的占空比会相应的增加或减少。-Controllable pulse generator of the VHDL source code. Design documents loaded to the target device and p
16weiyunsuanqi
- 16位运算器的设计和实现，具有参考价值，适合vhdl课设-16-bit computing design and the realization of a reference value for class-based vhdl
openmsp430_latest.tar
- how to design zigbee wireless product-how to design zigbee wireless product
LIP1601CORE_des_3des
- DES & 3DES VHDL & Verilog code
synchronous
- 1：10串并转换，包括同步检测和字对齐功能。-1:10 string and conversion, including the simultaneous detection and word alignment.