资源列表
gold_code_generator_rank10_b
- 通信扩频码GOLD码序列的产生，码长度可以手动设置，VHDL语音实现。-GOLD generate communication code sequence spreading code, the code length can be set manually, VHDL voice implementation.
time_check
- 通信主从机双向系统时钟同步，用于扩频、跳频等。由从机发起时间校准请求，主机回复时间信息，达到主从机的时钟同步。-Slave two-way communication between the host system clock synchronization for spread spectrum, frequency hopping and so on. Initiated by the slave time alignment request, the host response time
adc7854
- ADS7854 Texas Instruments. The code is built refer to the time sequence datasheet. You should better read the document first-ADS7854 Texas Instruments. The code is built refer to the time sequence datasheet. You should better read the docum
xilinx_DDR3_design_guide
- 关于FPGA的DDR3的设计和应用指导，是个很不错的文档，适应学习FPGA的人进行学习研究-FPGA DDR3 design and application guide
Proj_AND_V1
- Basic vhdl code for and gate logic.
contadorBCD
- 7seg decoder for the best displays
contador_off_board
- template of decoder for implemente in vhdl language.
spartan3e_test
- Teste Spartan 3e for Spartan 3e board.
VHDL-qiangdaqi
- VHDL语言实现的抢答器功能，源码和原理图都包含在文件内，可以直接在FPGA上运行。-The VHDL Responder function, source code and schematics are included in the file, you can run directly on the FPGA.
costas
- costas锁相环matlab仿真代码，对costas环的研究和硬件实现具有指导意义。-Costas Phase-Loop MATLAB Code.
wiegand
- Wiegand encoder Recive card number Save card number Mach saved and recived card number Resolve access status
fft
- 实现功能：基8实现64点FFT处理器（进行两次8点FFT计算，采用基8进行64点） 详细说明：硬件结构包括六部分，分别为输入模块、8点FFT模块、乘法模块、顺序调整模块、输出模块和总控制模块。 其中，输入模块的主要功能是将串行输入的64个数据进行分类，分成8批次，每次8个输入到8点FFT模块中进行计算。 8点FFT模块：FFT是DFT的快速算法，当点数较大时，可以较大的减少DFT的运算量。常用的FFT算法主要有两种，分别为按时间抽选的FFT算法（DIT-FFT）和按频率抽选的FFT算