资源列表
divider
- 移位快速除法器，通过一次移4位试商实现快速除法功能，较普通减除法器有及其巨大的效率提升-Divider rapid shift by a shift to four test functions of rapid division, as compared with ordinary objects have less efficiency and its huge
vhdlcodeforcalculator
- calculator using VHDL CODE
quartus.ii.11.0-crack
- 这是最新版的quartus11.0的破解文件，怎么做我就不说了，里面说的很清楚，我已经尝试，保证能用！希望大家学习愉快！ 另外此破解只做内部测试交流，切勿用于商业用途，否则后果自负，请勿广泛传播。-This is the latest version of the quartus11.0 the crack file, how do I do not say, which made it very clear, I have tried, guaranteed to last! Hope y
i2c
- I2C控制配置 WM8731芯片 FPGA-I2C control configuration
FIFO-verilog
- 两种异步FIFO设计以及源代码（Verilog）-Two asynchronous FIFO design and source code (Verilog)
serial
- VHDL实现串口控制逻辑源代码,包括各个模块的具体实现和元件例化-Serial control logic to achieve VHDL source code, including various modules and components to achieve the specific cases of
fpga
- 哈工大。计算机设计与实践课程测试FPGA。包括VHDL代码。ucf文件和.bit 文件。-Harbin institute of technology s corse. Computer Design..Homework3.
FPGA_examples
- FPGA工程例子.verilog HDL语言编写；-FPGA project examples. Verilog HDL language
vga
- VGA的时序及相关代码，通过它可以实现视频的VGA显示-the timing and vhdl code of vga.
pci-transmission-interface-design
- pci传输的接口设计的verilog，未用桥接芯片-pci transmission interface design verilog, unused bridge chip
Crack_QII10.0_x86
- Crack Alter Quartus 10.0
yinpin
- 这是全国一等奖作品音频信号分析仪的FPGA源码，该设计采用FFT的设计方法，其中FFT利用IPcore，采用的是burst流型的，减少了计算量，保证了频谱更新及时。-signala analysis by FPGA,by FFT