资源列表
PLL
- 采用Verilog语言，使用IP核的PLL，产生3种不同频率的输出，已测试验证通过-Using Verilog language, the use of IP cores PLL, produces three kinds of output at different frequencies, it has been verified by test
uart
- UART串口通信，50M晶振，256000波特率（从9600到256000可选），8位数据，1位开始，1位结束，没有校验位，测试稳定传输。-UART serial communication, 50M crystal, 256,000 baud rate ( 9600-256000 optional), 8 data bits, 1 start, an end, no parity bit, stable transmission test.
fpgaex5
- 测试反应时间，本例子是在DE2板上实现的测试人反应时间的程序-react time
FFTdesign
- FFT处理器设计及其应用研究，适合做fpga信号处理的技术人员参考-FFT processor design and applied research, suitable for signal processing fpga technology reference
licheng
- 有关数码管，定时器，ADC，方波生成器，电压比较器的，频率计等的程序学习样本-The digital tube, timer, ADC, square wave generator, voltage comparator, such as the frequency of the program study samples
BRAM
- 实现先进后出的RAM设计，并在屏幕中显示，用拨码键输入数据，VGA显示read和write和数字-After the realization of the advanced design of the RAM, and displayed on the screen, use the dial keys to enter the code data, VGA display and digital read and write
step_motor
- 2相混合式步进电机驱动程序，配套MC860H驱动器，共阴极接法 EN提前DIR至少5us，正常工作为高电平 DIR提前PUL下降沿5us确定其状态高或底，DIR 高：正转，底：反转 PUL脉冲信号，高电平不小于2.5us，低电平不小于2.5us(2 phase hybrid stepper motor driver, matching MC860H driver, common cathode connection method.EN advance DIR at least 5us, n
de2-sd-mp3player
- de2板上，先存入sd卡，实现的MP3播放器功能-de2，sd2，MP3player
10_I2C
- I2C是现代芯片和外设通信的常用方式，本例通过Verilog语言实现I2c通信-I2C chips and peripherals in modern communication methods commonly used, in this case through the Verilog language communication I2c
vhdl
- 非常经典的verlog hdl 语言学习教程及开发程序开发事例
BouncingBall
- VGA显示撞球游戏 硬件平台：DE2-70开发板 通过控制按钮可调节小球大小和运动速度-VGA display pool game Hardware platforms: the DE2-70 development board The control buttons can adjust the size and velocity of the ball
IEEE-standard-Verilog-HDL
- IEEE 标准 Verilog 硬件描述语言，这是IEEE 制订的verilog 标准参考文档-IEEE Standard for Verilog Hardware Descr iption Language