资源列表
DE2Project_restored
- 2006nios嵌入式系统电子设计大赛时用过的完整工程。-2006nios Embedded System Electronic Design Competition used when the integrity of the project.
1G-NANDP1G-DDR3-(Rev_01)
- 1G Bit (129Mx8) Nand flash / 1G Bit (8Mx16x8Banks) DDR3 SDRAM
cyclone_SignalTapII_Test
- cyclone SignalTapII 应用-cyclone SignalTapII Test
calculator
- 基于FPGA DE2开发板的计算器设计。Verilog语言编写。矩阵键盘输入，LCD1602显示。程序包括按键扫描模块、数值处理计算模块和LCD控制写模块等。-Calculator design based on FPGA DE2 development board. language use Verilog. Matrix keyboard input, LCD1602 display. Program includes key scanning module and LCD module
sw_bit8_latch
- 組合8個開關防彈跳,再加栓鎖電路,可讓開關動作更穩定-A combination of eight key anti-bounce, plus latch circuit allows the switching action is more stable
usb3.0
- USB的VHDL程序通过验证准确无误大家看看 看吧-USB through the VHDL program to verify the accuracy of all look at and see and see
DDR SDRAM Design Tutorials
- Altera公司的基于NIOSII设计DDR和DDR2内存的资料，很有帮助的，-Based on Altera' s DDR and DDR2 memory NIOSII design information, useful,
exp7_final
- CPU流水线设计 实现旁路 停顿 和 控制竞争处理 源代码-CPU pipeline design and control of competition to achieve bypass stop processing the source code
Oreilly.Programming.Google.App.Engine.Nov.2009.ra
- E-book: Oreilly.Programming.Google.App.Engine.Nov.2009
6_key_test
- 键盘按键，基于Quartus的用Verilog实现键盘扫描(The keys on the keyboard, Quartus keyboard scanning based on Verilog implementation)
Computer-Architecture-lab4
- 计算机组成实验作业4，fpga开发板，verilog语言编写-Composition of experimental computer operating 4, fpga development board, verilog language
TAXI_TOLL_1_1
- 实现出租车自动计费器 能进行LCD1602液晶显示。硬件平台：Xilinx Spartan3E -Use VHDL languange to achieve the automatic taxi meter and display cost,waiting time and distance on the LCD1602 . Hardware platforms: Xilinx Spartan3E