资源列表
IEEE Standard for Verilog 2005
- IEEE Standard for Verilog 2005
IEEE Standard for Verilog 2005
- this book introduces the use of Verilog HDL.
project_2
- 实现了基于FPGA的FFT变换，从最基本的32位2进制浮点数加减乘运算模块开始，组装出FFT模块。同时仿真文件中有32位浮点数转换为实数的仿真模块便于调试-Realized FPGA-based FFT transform, starting with the most basic 32-bit binary floating-point addition and subtraction multiplication module, a FFT module assembly. At the s
uart_test
- verilog写的串口发送机，虽然简单，但是注释写的比较清楚，适合新学习FPGA的同学作参考(Serial transmitter written in Verilog)
RS232
- RS232源代码，波特率可自由设置, 经调试完全正确。-RS232 code
1
- FPGA图像压缩代码，可以在nios2上实现。包括压缩和解压缩-FPGA image compression code that can be realized in the nios2. Including the compression and decompression
digi_clock
- 用verilog写的数字钟程序，已在altera公司的cyclone IV开发板上运行成功，很有价值-Digital clock using verilog written procedures for the company in altera cyclone IV development board to run a successful, valuable
02_buzzer
- verilog HDL 驱动蜂鸣器 驱动频率可调 驱动频率在1KHz时 无源蜂鸣器声音较大-this is a verilog file to driver the buzzer
led_fluid(DB)
- 实现可控制的流水灯，适用于Cyclone IV E EP4CE115F29C7芯片，可以使用按键控制启停，控制流动方向等。-Control light water and apply to the Cyclone IV E EP4CE115F29C7 chip, you can use the buttons to control the start and stop, control the flow direction.
FPGA2
- fpga初学者入门用提高fpga设计能力 尽快投入fpga开发-Beginners fpga fpga design capabilities improve as soon as possible with the input fpga development
reconfigurable-computing
- 面向图像处理的可重构计算系统结构 大连理工大学硕士论文 -For image processing reconfigurable computing architecture master' s thesis, Dalian University of Technology
led-water
- 流水灯程序，时钟频率为50MHz，控制四个led向同一个方向移动，如流水一样。没建个0.5s点亮一个灯，使灯亮朝一个方向移动-Water lights, clock frequency of 50MHz, control four led moving in the same direction, like water, like. Did not build a 0.5s lit a lamp, the lamp lights move in one direction