资源列表
Vivado--设计流程指导手册-(含安装流程与仿真)
- vivado设计流程指导文件，里面包含有软件安装流程以及仿真流程(Vivado design flow guidance document, which contains software installation process and simulation process)
yanjiusheng
- Optical communication
C51
- mc8051在xilinx nexys3上的移植，包括ROM和RAM-mc8051 xilinx nexys3
P
- 该工程实现了BDPSK调制器的设计，其中的主要模块有差分编码模块、分频模块、延时模块等。该工程在Quartus软件下运行。-The project implements the design of BDPSK modulator, the main module has a differential coding module, frequency module, time delay module etc.. The operation of the project in Quartus so
sdram_pci.rar
- 基于SDRAM的PCI采集程序，PCI9054控制器+SDRAM控制器Verilog源代码，，已经SignalTap调试通过。,SDRAM PCI-based acquisition program, PCI9054 Controller+ SDRAM controller Verilog source code, has SignalTap through debugging.
led_water
- 流水灯，Verilog编写，可用用，在quartus仿真过，也下载到FPGA开发板啦，可用。-Running water light, Verilog code, available to use, in the quartus simulation, also downloaded to the FPGA development board, is available.
eetop.cn_dds
- 基于verilog的DDS设计,内附代码,仿真环境等说明-the DDS design based on verilog
USB_Blaster_SCH_PCB
- 兼容ALTERA公司的USBBlaster下载线的原理图和PCB文件-ALTERA compatible with the company' s USBBlaster download line schematic and PCB files
DS18B20
- 本源码用verilog实现对DS18b20温度传感器的时序控制，使DS18b20能正常工作，获得温度数据-The source verilog of DS18b20 temperature sensor timing control, so DS18b20 can work to obtain temperature data
VERILOG
- verilog基础知识与快速提高练习,包括verilog的语法知识，以及一些基本操作-verilog
pulse
- 这是一个方波程序，在quartus平台编写，可以通过设置参数生成方波信号。(This is a square wave program, written in the quartus platform, you can generate square wave signals by setting parameters.)
counter
- 基于fpga的倒计时器。 可实现6位数的倒计时，通过按键设置初始值，倒计时结束提醒等功能(An inverted timer based on FPGA)