资源列表
dig_watch
- fpga实验，基于VHDL语言的数字跑表设计，其中包含有存储模块。-Fpga experiment, the digital stopwatch designed based on VHDL language, which contains a storage module.
hidejj
- 实现线性反馈移位寄存器的verilog实现(lfsr use verilog for the zip)
iir_16
- 用QUARTUS软件实现一个16阶的IIR滤波器-QUARTUS software with a 16-order IIR filter
jisuanqi
- 计数器PS2键盘输入LED VGA显示带声音-Counter PS2 keyboard input LED VGA display with sound
xilinx_labs.tar
- quick start EDK xilinx labs
led
- fpga的一个流水灯程序，芯片信号是ep4ce6f17c8n(A flow light program for FPGA.)
DIRECT-DIGITAL-SYSTHESIZER
- Direct digital systhezier on FPGA WRITTEN WITH VERILOG
ethernet_tri_mode
- Its an verilog coded ether net tri mode project
三速以太网代码（FPGA）
- 本代码是运用xilinx的fpga实现千兆网的，同时支持百兆以太网和10兆以太网。内含仿真文件
ring_fifo
- use Sram with ring fifo Spartan-3
01d47c3acce2142620ee6758c98d5938
- //时钟是48Mhz,所以16*9600的分频数为312.5,这里取整-while(1) k++ if (k==100) k=0 next
verilog_EXAMPLE
- verilog编写的例程指导，包括入门教程和一些设计实例-verilog routines written guidance, including the Getting Started tutorials, and some design examples