资源列表
LCD_CLOCK
- 用1602液晶显示的数字电子钟，并且可以用按键开关调整时间，日期，星期。-1602 LCD display with digital electronic clock, and the key switch can be used to adjust the time, date, week.
FPGA_verilog_uart-
- 基于 FPGA器件设计实现UART的波特率产生器、UART发送器和接收器及其整合电路,，利用Veriolog-HDL语言对这三个功能模块进行描述并加以整合，通过ModelSim仿真，用串口调试程序进行验证，最终实现一个通用异步收发器的设计。-UART baudrate generator, transmitter and receiver and its integrated circuit are implemented by FPGA device. Using Veriolog-HDL d
SDRAM-controller-design-FPGA-based
- 基于FPGA的SDRAM控制器设计及应用硕士论文-SDRAM controller design FPGA based
led
- 利用计数器设计延时函数，通过四个led灯的闪烁，可以直观观察延时时长，fpga器件cyclone iv LCMXO2-1200HC-4TG144CR1,在demo板上作简路图(Using the counter to design the delay function, through the flashing of four LED lights, we can observe the delay time directly, FPGA device cyclone IV LCMXO2-12
VerilogHDL-and-CPLD-programmin
- 从零开始学CPLD和VerilogHDL编程技术，包括实验板原理图和实验源代码。,VerilogHDL learn from scratch and CPLD programming technologies, including board schematics and test source code.
cpuVHDLshixian
- 很好的程序 调试通过能够轻松运行 可以在环境里 简单编译通过 -that is good sources
国产FPGA参考设计IPCORE_UART_example_M5&M7
- 国产FPGA的UART参考设计IPCORE源代码。 The IP provides two kinds of simplified interface connected to EMIF bus and AHB bus for communication with 8051 core and ARM core.The two kinds of interface are full-duplex serial communication interface. Support programmabl
USB2_36M
- USB的驱动程序，能直接使用于FPGA与上位机USB接口的连接-USB driver, can be directly used in FPGA and USB PC interface
clock_display
- 自己用verilog语言编写的数字钟程序，能在Alter公司的DE0板上完美运行，能时间计时，日期，闹钟，秒表的功能。 欢迎交流学习。-The digital clock program which developed by verilog language can run at Alter DE0 board, to the time time, date, alarm clock, stopwatch function.
DE2_115_Default
- DE2-115板出厂时带有一个默认的配置位流，它演示了板的一些基本特性。(The DE2-115 board is shipped from the factory with a default configuration bit-stream that demonstrates some of the basic features of the board.)
wavemaker
- VHDL做信号发生器：包括三角波、正弦波还有锯齿波-wavemaker-> Tri wave &Sin wave &Saw wave
h264_2008
- 编解码的算法优化研究及FPGA的硬件实现-encoder fpga