资源列表
eulemethod
- Eules s method code - matlab
yinbo
- 密码锁，输入正确的密码门开，错误的密码灯亮，连续输入三次错误的密码，发出报警声，直到输入正确的密码-Password lock, enter the correct password the door opened the wrong password lights, continuous input an incorrect password three times, alarm sound, until you enter the correct password
FFT_4
- FFT4 Algorithm for ldpc
20130517
- 采用cpld控制ads8364实现六通道采样，采用verilog语言-Cpld control ads8364 six-channel sampling, using the Verilog language
my_zbt_controller
- ZBT内存控制器.支持OPB总线。VHDL源码
vga_teste
- This code allows an application with VGA using VHDL
filter_200us
- 此为Verilog编写的延迟200US的程序，为Verilog常用模块。-This is written in Verilog delay 200US procedures used for the Verilog module.
de4
- this code can be implement on De2 and De2-70. -this is a source code for de2 that can simmulate SIMP08.
TEXTIO_Import_txt_Matlab
- 将FPGA设计仿真结果数据写入到txt记事本中，然后通过Matlab读取txt中的数据并显示图像-write the FPGA simulation result data into textbook,and read these data from textbook and display image in Matlab
cal
- verilog设计计算器顶层模块，无下层模块需自行添加-verilog based calculator
mcst
- 曼彻斯特编码实现，verilog HDL 做的，我也是从网上下的-Manchester encoding to achieve, verilog HDL to do, I am also from the Internet under
uart
- 用VHDL实现的一个uart控制器，输入时钟为33M-Use VHDL to achieve a UART controller, input clock for the 33M