资源列表
bin_copy
- FPGA驱动12864汉字显示源代码，12864是16个引脚的带字库的液晶显示模块-12864 Chinese character display FPGA-driven source code, 12864 is a 16-pin LCD display module with a font
ddslabview
- The reference design and example presented in this article illustrates how you can add a DDS (direct digital synthesis) waveform generator to your LabVIEW FPGA based applicationThe examples for this article are contained in a LabVIEW 8.5.1 project.
de2_115_sram
- 基于quartus13.1在DE2_115平台下进行了SRAM的测试开发，功能虽然简单，但是代码风格很好，封装性很好！应该学会模块化书写程序！-DE2 115 SRAM QUARTUS13.1
project3
- mips single cycle cpu
DE0_NANO_VGA
- ntity DE0_NANO is Port ( CLOCK_50 : in STD_LOGIC --//////////// LED ////////// LED : out STD_LOGIC_VECTOR(7 DOWNTO 0) -- --//////////// KEY ////////// KEY : in STD_LOGIC_VECTOR(1 DOWNTO 0) -- --//////////// SW ////////// S
NIOS-II
- 关于NIOS II软件学习的资料，希望对大家有所帮助。-NIOS II software to learn about the data, we want to help.
uart_rx
- FPGA实现串口接收功能 Verilog语言-Serial reception FPGA Verilog language
ex5
- FPGA测试频率，传统测频率,verilog语言，短程序，测频法测频率(using FPGA verilog language a short code for frequtents)
cf_fft
- 用verilogHDL写的实现4096点FFT的算法，附带quartus ii工程.-VerilogHDL achieved with 4096-point FFT written algorithm works with quartus ii
x7seg
- 一个实用的FPGA数码管显示驱动，移植性比较好，Verilog语言编写，实测通过，可直接作为子模块调用-A practical FPGA digital display driver, portability is better, Verilog language, measured by, as a sub-module can directly call
uart
- 本设计用接口芯片的VHDL的设计方法，通过对MAX232串行通总线接口的设计，掌握发送与接收电路的基本设计思路，并进行串口通信-This design using VHDL design methodology interface chip, through the MAX232 serial communication bus interface design, master the basic design ideas to send and receive circuits, and se
ppscode
- verilog代码，输出秒脉冲，用于采集同步-verilog code, second pulse output for synchronization acquisition