资源列表
LCD
- 用verilog 实现的液晶屏驱动程序，已多次应用于项目中.经测算，性能非常稳定可靠。-Verilog achieve with LCD driver, it has repeatedly applied to the project. After calculation, the performance is very stable and reliable.
uart_tx
- FPGA实现串口发送 Verilog 语言-Serial reception FPGA Verilog language.
signal-generator
- 关于任意信号发生器的一些设计,以及具体的电路图，时钟，DA转换-signal generator
Exam-I
- FPGA VHDL comparator
TLC5615_1k
- 进阶实验_12_DA[TLC5615]_1：通过DA输出正弦波，频率1KHz-Advanced experimental _12_DA [TLC5615] _1: By DA output sine wave, frequency 1KHz
Day4
- 关于FPGA的文档，通过此文档可以更好的学习FPGA的运作和开发。-Documentation on the FPGA, through this document can better learn the operation and development of FPGA.
audio on fpga
- THis is the project that demonstrate the audio system on fpga basement. From this starting piont, other researcher can develop their own project easily
uart_state
- 基于状态机编写的串口通信实验，编程语言是Verilog HDL，可发送八位数据，在Altera的EP4CE15F17C8芯片上验证成功。（与另一个发送256位不同的是这个代码比较突出状态机的使用）。-Prepared by the serial communication experiment based on state machine, the programming language is Verilog HDL can transmit eight bits of data, verif
key_xiaodou
- 这是消除抖动源代码的关键，适合刚刚学习vhdl的新手，按键消抖是需要掌握的一课-This is the key to eliminate shaking the source code, suitable for just learning vhdl novice, key to eliminate shaking is a lesson in the need to master
alarm
- 利用verilog语言 写成的 倒车报警系统的源程序 基于 cyclone系列的FPGA-Using verilog reversing alarm system written in the source code of the FPGA-based cyclone Series
FT3_crc
- FT3发送程序加CRC校验,曼彻斯特编码-FT3 sender plus CRC, Manchester coding
SynplifyPro_Quartus_v5_v4_1
- Quartus仿真软件SynplifyPro应用指导-Guidance on the application simulation software SynplifyPro Quartus