资源列表
lcd
- spartan3E开发板LCD开发程序，调试通过-spartan3E development board debugging
USB_Verilog_IP
- USB IP核VHDL源码(使用VHDL实现的USB IP core)-USB IP core VHDL source
OOB_control
- 串行传输协议sata的物理层的控制模块的状态机-Serial transmission agreement of the physical layer control module sata the state machine.
minus
- 一位二进制全减器的设计，分别用原理图输入法和文本输入法，用分层设计的方法完成-A binary full subtractor design, respectively, schematic input and text input method, complete with a hierarchical design method
xsp605_ilinx_mig_ipcore
- 赛林思开发板sp605的内存管理单元的ip核调试通过-SP605 IP core mig
v_verilog
- Verilog VHDL经典实例，完整源码与大家分享。-Verilog VHDL classic example of a complete source to share with you sponser links.
verilog2
- 用verilog语言编写的按键消抖程序。通过下降沿检测法可以判断出是否按键。压缩包内也包含此按键消抖程序的modelsim仿真文件。-Verilog language with key debounce process. By falling edge detection method can determine whether the key. This compressed package also contains procedures for key debounce modelsim
test12864
- 12864的VHDL程序！测试成功的！ -12864 VHDL program! Test successful!
uartverilog
- verilog hdl FPGA vga时序显示经典源程序 很实用的-verilog hdl FPGA vga display timing source code very useful
FT245RW
- 用virilog语言在quartusII下实现FPGA与FT245BL芯片通讯-realize the communication between FPGA and FT245BL.
b_pro3_restored
- 2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码，分信号源和分析仪两部分-2011 electronic design competition e question the simple digital signal transfers analyzer "verilog the source code, and the points the signal source and the two parts analyzer
VgaSnake
- 贪吃蛇+vga显示。有暂停、继续功能。Xilinx开发-Snake+ vga display. Pause, continue to function. Xilinx development