资源列表
RT_Ethernet
- 实时以太网MAC层协议控制器。注：100M全双工-Real-time Ethernet MAC layer protocol controller. Note: 100M full duplex
VHDL_Sample
- VHDL VGA彩条发射器，里面有4个文件，分别是直接输出的，还有通过ROM查找颜色的，通过RAM和DRAM的-VHDL VGA color of the transmitter, there are 4 files, namely, direct output, as well as to find color by ROM, RAM and DRAM through the
FIFO_1
- 利用FIFO模块实现不同时钟模块间的传输(The transmission between different clock modules is realized by using FIFO module)
IEEE_Standard_verilog_std_1364_2005
- And here is the latest standard for you to read and use! everything for u!
filter
- 如何利用verilog设计数字滤波器 包含低通滤波器,带通滤波器,高通滤波器.-how to design a digit filter with Verilog
verilog
- 上海交通大学不错的verilog 教程。-Shanghai Jiaotong University, good verilog tutorial.
nco
- 基于FPGA的压控震荡器，可以通过震荡器来对输入信号进行有效的分频，而且是任意的分频系数都可以-FPGA-based VCO oscillator input signal, the effective frequency division and any sub-frequency coefficients can be
dds
- 基于FPGA，利用vhdl语言结合matlab工具实现dds,已经仿真-Based on FPGA, VHDL language with matlab tools to achieve DDS, has simulation
vhd2v
- vhdl与verilog之间的语法区别 以及滤波器设计-grammatical distinction between vhdl and verilog filter design
seg
- 四位一体数码管显示，实现数码管动态显示。已经测试，很好用！-Four digital tube display, realize the dynamic display of digital tube.Already test, very good!
fpgaexperiment
- 总共包括7个实验，SRRAM测试，按键及PIO口中断实验，定时器实验，seg7实验，sopc_led实验，FLASH少些，FPGA_led,锁相环。-Including a total of 7 experiments, SRRAM test, test buttons and PIO port interrupt, timer experiment, seg7 experiment, sopc_led experiment, FLASH less, FPGA_led, PLL.
pro
- S10420背照式CCD verilog 状态机驱动代码-S10420 back-illuminated CCD verilog state machine driver code