资源列表
jpeg
- JPEG(Joint Photographic Expert Group,联合摄影专家组)编码的数据执行解压缩的各项功能.JPEG的VHDL实现代码-JPEG (Joint Photographic Expert Group, Joint Photographic Experts Group) encoding of data to implement the various functions of decompression. JPEG realization of VHDL code
spartan2e_and_spartan3_xc2s300e-6pq208
- spartan2e 和spartan3以及spartan2e系列芯片的xc2s300e-6pq208的资料（datasheet）-spartan2e and spartan3 and spartan2e series chip xc2s300e-6pq208 data (datasheet)
VGAterm
- simple thermometr in vhdl
Complexdigital-circuits
- 复杂数字电路与系统的VerilogHDL设计技术-Complex digital circuits and systems design techniques VerilogHDL
ncvlog
- Cadence NC-verilog user guide C adence NC-verilog user guide C adence NC-verilog user guide Cadence NC-verilog user guide-Cadence NC-verilog user guide Cadence NC-verilog user guide Cadence NC-verilog user guide Cadence NC-verilog user gu
pci9056db-091b_296305
- PCI9056芯片详细资料。包含有12章的内容，全英文版。-PCI9056 chip detailed information. Contains a chapter 12 of the content, the English version.
FPGA--TimeQuestREV2.0
- FPGA那些事儿--TimeQuest静态时序分析REV2.0，这个不用多说了吧，经典之作，大家多多学习，共同进步~~这个是版本2-FPGA that thing- TimeQuest static timing analysis REV2.0, this goes without saying it, classic, everyone can learn together and progress ~ ~ This is version 2
qdq_ise9migration
- 六人抢答器是旨在模仿答题抢答过程中选手抢答，答题倒计时，主持人控制以及数字清零等步骤。原则上算作是模拟仿真类动手实验，设计难点有筛选抢中的选手，抑制有选手违规抢答，主持人控制答题以及抢答时间，强中或者答题时间到的报警时间，以及在大屏幕上显示时钟倒计时以及抢中的选手编号并且对LED灯进行复位。-Six Responder is designed to mimic the answer in the answer in the answer in the process of players,
ethernetblaster-200-202-gpl.tar
- ALtera网络Blaster的映射文件-Altera network mapping document Blaster
DE2_PC
- DE2板与pc机通信过程，传输图片文件。-communication between DE2 and PC。
FPGA_timing
- FPGA最重要的就是时序收敛，本资料重点介绍的就是FPGA设计时序收敛，从培训班带过来的资料，讲得非常好，强力推荐~-FPGA timing closure is the most important, the information is focused on FPGA design timing closure, brought over from the training data, made it very good, highly recommended ~
A01
- 利用XC9572-TQFP100(Xilinx CPLD)制作的多功能CPLD/FPGA的ISP下载线源代码及线路图。可用来烧录Xilinx,Lattice,Altera等厂家的CPLD/FPGA.-Using XC9572-TQFP100 (Xilinx CPLD) produced by multi-CPLD/FPGA download cable ISP in the source code and circuit diagram. Burning can be used to Xilin