- Charting_src Report Control is used for the features of List Ctrl
- MATLABjiyudiandetuxiangpeizhun 应用基于点的方法
- 10509019_final.pdf design and implementation of faster and low power multipliers in vhdl
- board-dt-sam9 Setup code for AT91SAM Evaluation Kits with Device Tree support.
- allocator_test Lets try to allocate almost 4096 Go (on most of the platforms) of memory:.
- jfree-demos-master jfreechart
资源列表
cf-fft
- 用ip核实现fft。用vhdl编写。altera的fpga-Ip core implementation using fft. Written in vhdl
fft
- 基于fpga的fft变换，用ip核实现。用vhdl编写-Fpga based fft transform, use ip core implementation. Written in vhdl
gensin
- 用fpga控制da发一定带宽正弦信号，用vhdl编写，用nco-Fpga controlled by a band-da made a sinusoidal signal, written in vhdl, with nco
pipelined_fft_256
- pipelined fft/ifft 256 point ip core
SHA3-VHDL
- SHA3 VHDL implementation FPGA proven
sqrt_32bit_non_restoring
- a 32bit non-restoring square root with CSM in VHDL
Sequence-Detector
- 序列检测器，开写为两个always语句，即为两段式有限状态机。将组合部分中的判断状态转移条件和产生输入再分开写，则为三段式有限状态机。 二段式在组合逻辑特别复杂时适用，但要注意需在后面加一个触发器以消除组合逻辑对输出产生的毛刺 。三段式描述方法虽然代码结构复杂了一些，但是换来的优势是：使FSM做到了同步寄存器输出，消除了组合逻辑输出的不稳定与毛刺的隐患，而且更利于时序路径分组，一般来说在FPGA/CPLD等可编程逻辑器件上的综合与布局布线效果更佳。-Sequence Detector
Spread-Spectrum-Analyzer
- Spread-Spectrum-Analyzer in verilog with testbench
binarytree
- Binary tree in system verilog using classes, and automatic function
uart
- Atmega 328 UART clone with testbench, cannot be synthesized to gates
The-first-edition-oscilloscope
- 第一版魏坤手持开源示波器-The first edition open sourse handheld oscilloscope
Spring_2011
- 魏坤开源手持示波器2011春季版-WeiKun Open Sourse Handheld Oscilloscope Spring 2011