资源列表
HA
- Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
shuzizhong
- 基于VHDL的数字钟的设计，本文给出了详细的代码，直接可用！-VHDL-based digital clock design, this paper presents a detailed code, directly available!
Intersection-traffic-lights-control
- 基于FPGA的十字路口智能交通信号灯控制系统的VHDL程序代码-FPGA the crossroads of intelligent traffic signal control systems-based process and VHDL code
cordic_pipelined
- CORDIC算法的流水线verilog HDL实现，包含modelsim仿真所需的设计文件与testbench。-This is an implementation of CORDIC algorithm in verilog HDL, which contains design code and testbench.
nihonddeng
- 用VHDL实现16个霓虹灯按照多种方式闪亮.
demux
- 与多工器功能相反，可将一个位元的资料透过选择分配输出端的其中一个。 -In contrast with the multiplexer function can be a bit of information on the allocation of the output by selecting one of them.
AD
- AD采集控制时序,控制对象AD1674启动和转换-AD acquisition control timing, control object AD1674 starts and conversion
half_band
- 半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考-Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference
CfgDDS_9910
- dds ad9910配置的verilog hdl程序，模块化设计，输入待配置的数据，字长，启动信号，即可自动产生时序，完成一次配置，模块还有done握手信号，方便用户调用时，反复多次配置。-dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatical
jdcbzh.使用VHDL语言实现串并转换模块的实现
- 使用VHDL语言实现串并转换模块的实现，可在QUARTUS上实现,Use VHDL language string and conversion module, but in QUARTUS
lcd_timing_controller
- DE2-70 ltm timing Controller
uart
- uart send resive module