资源列表
fir6dlms
- lms算法，自适应滤波器中使用fir滤波器对信号的码间干扰进行均衡-lms
mc3208
- Get 8 A/D ADC mcp3208 by VHDL-Get 8 A/D ADC mcp3208 by VHDL
clock
- 这个程序是用verilog hdl语言编写，实现在数码管上显示时间，暂不支持调整-This program is written in verilog hdl to achieve in the digital tube display time, withhold support to the adjustment
aiqingmaimai
- 数字钟蜂鸣器音乐——爱情买卖，很时尚的闹钟音乐代码，经测试，很有感觉。-Digital clock buzzer music- love trading, very stylish alarm clock music code, tested, great feeling.
Broadcast_filter
- mac_rx code which is used sgmii mac recived .
spi_hello
- SPI接口测试程序，Xilinx参考设计，ML507硬件测试通过.-SPI interface test code，Xilinx reference design，tested on ML507 platform.
ControlCell
- verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
state
- 带正负的同频率周期信号的相位差测量机的FPGA实现-With positive and negative periodic signals with frequency phase measuring machine FPGA Implementation
tristate
- VHDL code for a full adder and n bit full adder a tri state buffer and a flip flop
spi_verilog
- spi接口设计源代码，实现了spi的接口电路，便于硬件升级-spi interface design
ad5544
- 模数乘法器AD5544的Verilog源程序，已在项目中验证了其可行。-Verilog source AD5544 analog multiplier, and have verified its feasibility in the project.
atan
- 自己写的cordic 的 64位计算反正切的程序，-cordic count atan program