资源列表
eatfish
- vhdl语言，可以实现大鱼吃小鱼功能的时钟仿真仿真，经过测试可用-vhdl language, can achieve ones devour function clock simulation simulation, tested available
ram_3
- RAM的verilog描述，包含向量名定义，顶层设计等等的精确描述-RAM in verilog descr iption, including vector name is defined, an accurate descr iption of the top-level design, etc.
dcm2
- 基于Xilinx Vertex4的可综合的二级DCM模块源代码，可生成400Mhz时钟信号-Based on Xilinx Vertex4 of two integrated DCM module source code, can generate 400Mhz clock signal
lcd_controller
- 本程序用VHDL语言实现LCD显示“hello，world”的功能，适用于ISE软件-This program with VHDL language LCD display " hello, world" functionality for ISE software
Digit_sys_proj-tbird
- T-bird LED by modelsim 6.5e
FILTER
- VERILOG CODE FOR 1D FIR FILTER IMPLIMENTATION -VERILOG CODE FOR 1D FIR FILTER IMPLIMENTATION
fft
- 基于FPGA的FFT 基于FPGA的FFT
allume_LED
- a simple exemple of vhdl for show the power of fpga card
multiplier
- vhdl code multiplier
dfre
- 在对信号频率进行测量的研究过程中，设计了三个测量档位，在不同的档位的到频率的精确度也不同，并且选择不同档位，相应的小数点的位置也不同。-In the study to measure signal frequency, the design of the three measuring stalls in different stalls to the frequency accuracy are different, and the choice of different stalls, th
ADF4106
- Management of synthesizer ADF4106
ROM
- 本代码实现的是生成随机数的verilog 代码。可在ModelSim中仿真-The code is the verilog code to generate random numbers. In the simulation in the ModelSim