资源列表
sign_square
- square wave form generator for vhdl
test
- 自己编的一个检测信号上升沿后处理，并延时分频处理的程序，已经仿真成功。-A rising edge detection signal own series of post-processing, and handling delay procedure divide has been successful simulation.
risc64
- Risc 64 - Bit Verilog Code
risc32_datapath
- Risc - 32 Bit Datapath Only
DM134b_Test
- 点晶DM134B恒流驱动芯片测试程序，包括20mA和40mA测试，FPGA采用LATTICE的M4A5-Point crystal DM134B constant current driver IC testing procedures, including the 20mA and 40mA test, FPGA using M4A5 of LATTICE
VHDL7
- 一个VHDL按键消除抖动以及显示的程序，让你明白按键消除抖动的原理。-A VHDL button to eliminate jitter and display procedures, so that you understand the key principles to eliminate jitter.
stimulus
- examples vhdl descr iption
aFifo
- 很好用的异步FIFO设计代码，和大家共享一下，这是我在一个美国的网站上找到的-Asynchronous FIFO design with good code, and share how this is an American site I found on
DA_FIR_VERILOG
- 基于DA算法的FIR滤波器的verilog实现-DA-based FIR filter algorithm to achieve the verilog
qam16
- QAM16是数字调制方式中最为常见的 方式之一，这里的Verilog 文件可以在 FPGA上实现的。-QAM16 digital modulation scheme is one of the most common ways here Verilog files can be implemented on the FPGA.
m2enc
- the attached code is the vHDL descr iption for implmenting Manchester logic with reference to HD6408 datasheet.
lcd
- 本代码利用verilog语言写的驱动LCD1602 其中LCD1602显示为英文。（LCD带字库）-This code is written in verilog use drive LCD1602 Which LCD1602 display in English. (LCD with font)