资源列表
testadder
- VHDL语言编写的加法器与测试代码，测试可用-Adder VHDL language and test code, the test can be used
fec_enc
- 实现RS（255，239）的编码器，语言为Verilog。-Implementation RS (255,239) encoder, language is Verilog.
sin
- 用vhdl语言编写的余弦函数，-Vhdl language with the cosine function. . . . . . . .
FPGA-VIRTEX5-VHDL
- XILINX Virtex5 关于演化硬件的VHDL代码-XILINX Virtex5
AD9863_if_old-2005-5-8
- fpga开发的程序，内容都不错，主要是ad
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising
e2prwctrl
- EEPROM芯片读写控制器的VHDL语音程序设计-EEPROM chip to read and write controller VHDL Voice program design
Game777
- Game 777. Have fun :)
ADC
- AVR单片机的ADC转换功能，详细注释，适用于初学者-AVR microcontroller ADC conversion function, detailed notes for beginners
FIR_Direkt_BAB_P
- VHDL编写的代码。采用流水线方法实现的FIR滤波器。22阶。Fa=48kHz, Fc=10KHz。可用ModeSim仿真并FPGA实现-Code written in VHDL. Line method using the FIR filter. 22 bands. Fa = 48kHz, Fc = 10KHz. Can be used to achieve ModeSim simulation and FPGA
matlab_quartus
- 用于matlab和quartus的联合开发-For the joint development of matlab and quartus
digital-filter-simulation
- 数字滤波器设计把整个设计方案用VHDL语言进行了描述并在Modelsim上仿真。-digital filter IIR Matlab VHDL Modelsim simulation