资源列表
startstopwatch
- 运动计时器的设计（1）在四个七段LED数码管上显示分钟和秒，最长的计时时间为59：59。 （2）按下清零按键，在四个七段LED数码管上显示的时间为00：00。 （3）按下启动/暂停按键，则启动或暂停计时器计时。其功能与实际的计时器的开始/停止按钮功能相同。设计一个能显示分、秒的计时器。在四个七段LED数码管上显示出来。-Sports timer design (1) in the four seven-segment LED digital display minutes and sec
Fibonacci-Sequence
- Fibonacci Sequence VHDL code.
LTC2440_1
- 一款具有 5ppm INL 和 5μV 偏移的高速 24 位无延迟增量累加 (No Latency ΔΣTM) ADC LTC2440的源代码-A 5ppm INL and 5 V high speed 24 bit offset without delay increment accumulation (No Latency TM ADC LTC2440 delta sigma) source code
Control_AD9516
- 时钟芯片AD9516配置代码，VHDL开发，可仿真验证-Development, clock chip AD9516 configuration code, VHDL simulation
ca
- 基于vhdl/verilog的gps接收机伪随机码产生程序。已经过仿真综合。-Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
Infra1_top
- 在FPGA上实现红外传输写的顶层文件，望大家给与意见，-In the FPGA to achieve the top-level document written by infrared transmission, hope you give advice, thank you
verilog.tar
- counter.v...its verilog code for counter
basic-vanding-code
- basic vandig code vhdl
fir5k
- 通带为4500到5500的带通fir的VHDL程序，经实践检验可用-Passband for the 4500-5500 bandpass fir of VHDL procedures, can be used by the practice
shumaguanxianshishizhong
- 数码管显示时钟的VHDL源程序，在数码管上显示时钟信息。-VHDL Source Program of Numerical code Tube Demonstration
DlFIFO
- Fifo for everyone :)
code
- 可编程器件课程实验相关代码。硬件描述语言中不同的描述，会综合出不同的硬件电路。-The programmable device curriculum experiments relevant code. The descr iption of the hardware descr iption language, will be integrated hardware circuit.