资源列表
Dff
- D 触发器，数字电路中最基本的逻辑单元之一。很实用的程序例子-D flip-flop, one of the basic logics in the digital design, an instance of a Sequential VHDL codes
conditioner
- VHDL设计的空调系统有限状态自动机，带有VHDL测试平台代码-VHDL design of air-conditioning systems finite state automata with VHDL testbench code
jiaotongdeng
- 以FPGA为开发平台的交通信号系统，带有倒计时和蜂鸣器功能。-To FPGA development platform for the traffic signal system, with a countdown and the buzzer function.
Basys2_100_250General
- Spartan 3e basys2管脚控制文件-Spartan 3e basys2 Pin control file
UART_send
- 串口单字节发送数据。已测试通过。编程预言是Ｖｅｒｉｌｏｇ。-Single-byte serial transmit data. It has been tested. Programming language is Verilog.
jiaotongdeng
- 这是用VHDL语言编译的交通灯程序，十分好用
verilog 写的 电话计费器程序
- verilog 写的 电话计费器程序 ,verilog to write a telephone billing program
all_cpu_scheduling
- the program gives cpu scheduling implementation
VHDL_4bit_magnde_compar_code_dataflow
- this is a source code for a 4 bit magnitude comparator using dataflow technique a 4 bit magnitude comparator logic circuit.-this is a source code for a 4 bit magnitude comparator using dataflow technique a 4 bit magnitude comparator logic circuit.
plldigitalclock
- 此文件是FPGA中数字时钟开发，包括时钟的分拼 ，备品-file is a digital clock FPGA development, including the sub-clock fight, spare
steppermotorVHDL
- 一种全新的VHDL控制步进电机驱动代码，以供学习-a new VHDL controlled stepper motor driver code for learning
IBM_PC
- This code allows you to read character from keyboard IBM PC