资源列表
crc16_8
- crc16,数据位宽为8，verilog编码-crc16 ,datawidth is 8,coding by verilog
chuzucheVHDL
- 用VHDL写的出租车计价程序，拥有详细的说明-Taximeter written with VHDL program, has a detailed descr iption of
QDEC
- 旋转编码器的正交解码程序，使用VHDL语言--- This decoder in VHDL samples the signals using all four available edges of -- A and B. E.g. sample(B) on rising(A), sample(A) on falling(B), sample(B) on -- falling(A), and sample(A) on rising(B).
fir
- FIR滤波器的FPGA实现，串行移位算法，运行周期长但资源利用率低。-FIR filter FPGA, serial shift algorithm, but the long-running cycle of low resource utilization.
addersubtractor
- 可以实现加法和减法的VHDL源码，可以在FPGA上运行
3
- 3對8解碼器 可提供3線8選擇之功能 可輕易改成4選16-Three pairs of 8 decoder may choose to provide 3-line 8 of function can be easily changed to 4 election 16
ad9777_ini
- Verilog编写的AD9777初始化代码-Verilog code to initialize the preparation of the AD9777
Flash
- 三星flash编程Verilog程序，单页编程，支持K9K4G08芯片-Samsung' s flash programming Verilog program, single-page programming, support K9K4G08 chip
encoder_1553
- quartus软件编写，1553总线编码的程序-The quartus Software written in 1553 encoding program
verilog_latch
- verilog实现锁存器，共有四个文件，包含测试文件-verilog achieve latches, a total of four documents, including test paper
LED
- 基于Verilog小程序，在LED上交替、轮显爱心形状-display on LED
ControlUnit
- Control Unit VHDL code. Xilinx Spartan 3E board