资源列表
50M
- verilog 语言写的分频模块，实现用50Mhz的时钟频率分出1hz的频率，也就是一秒的频率-verilog language sub-frequency module, using the 50Mhz clock frequency 1hz separation, that is, the frequency of second
stopwatch
- 基于fpga的停表设计vudl编写，使用vhdl编写的.v文件。-the stopwatch based on fpga written with vhdl
Finit_state_machine_in_C
- C实现一个状态机,我做毕业设计，实现自组织网络，三个节点-Finit state machine implemented in C code
32-rip-adder
- A ripple carry adder allows you to add two 32-bit numbers
26204298SRAM-PINGPANG
- 一个用verilog写的简单的乒乓球程序，用来在VGA上显示小球和挡板-Using Verilog to write a simple table procedures, used in the VGA display of small ball and baffle
shift-register
- VerilogHDL语言实现的普通寄存器-VerilogHDL language common register
LCD16x2 Interfacing
- This source VHDL code is used for control LCD16x2 on FPGA
lcd
- This source is used to control LCD 16x2 on FPGA board
state_classic
- 用VHDL语言编写的语言,可以利用MODELSIM进行仿真.对于初学者,则更有参考价值.-prepared using the VHDL language, we can use MODELSIM simulation. For beginners, the more valuable reference.
bcd
- EDA 十进制计数器、BCD VHDL源代码-EDA decimal counter VHDL source code
FIR
- The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. Th
myinterpolation
- 复杂的插值函数，用于颜色空间转换 verilog-The complex interpolation function for color space conversion verilog