资源列表
booth_mult
- 布斯乘法器的verilog实现及仿真文件,使用modelsim仿真-booth mult s verilog and test
clk_div
- 通用异步接收/发送装置。实现微处理器与外微设备的串行通信-Universal asynchronous receiver/transmitter device. Microprocessor and external Micro Devices serial communication
telephone-cost-metering
- 该程序用来实现电话计时以算取费用，比较简单-telephone cost metering verilog code
mult
- verilog编写的8x16常变量乘法器，可用quartus仿真-verilog prepared 8x16 often variable multiplier, available quartus simulation
vga
- vga实现汉字显示，只有。v和ucf文件 基于sprtan3e板-vga word print
alu64_struct
- 六十四位ALU设计源代码，可实现加减，逻辑与，或等多种功能。-64 ALU design source code can be modified to achieve, and logic, or other functions.
12864
- 用VHDL 语言驱动DM128*64LCD程序
fir_gen
- fIR（有限冲击响应）滤波器基于vhdl语言开发-FIR filter
tb
- 八线译码器的源文件程序用三态门控制其输出输入-entity eightbitcounter
pljfpja
- 频率计的fpja部分程序，，，用高精度测频法实现。。。能测1、、1M-frequency of fpja some of the procedures, and using high precision frequency measurement method to achieve. . . Can be measured one, and 1M
FPGA-based-system-
- 此程序实现了基于FPGA的车载DVD位控系统的显示与输出模块的设计。-This program implements an FPGA-based digital control system, Car DVD display and output module design.
divider
- 使用模为2N+1的计数器,让输出时钟在X-1(X在0到2N-1之间)和2N时各翻转一次,则可得到奇数分频器,但是占空比并不是50 -The use of modulo 2N+1 counter, let the output clock in the X-1 (X between 0 and 2N-1) and 2N of the turning once, then can get the odd divider, but the duty ratio is not 50