资源列表
FSM
- 用verilog语言编写的FSM文件，有限个状态及在这些状态之间的转移和动作等行为的数学模型，在计算机领域有着广泛的应用。-Mathematical model with verilog language FSM file transfer and finite number of states and actions between these states and other behavior in the computer industry has a wide range of appl
mp3if
- 通过CPLD将8位并行数据转换为串行数据并可以采用I2C方式与其他器件连接，可以用于MCU需要与提供I2C接口器件通信的场合。-through CPLD to eight parallel data into serial data and methods can be used I2C connections with other devices, which can be used to provide MCU with I2C Interface Communications occasi
ADCINT
- 此程序基于ADC0809,它是CMOS的8位A/D转换器，片内有8路模拟开关，可控制8个模拟量中的一个进入转换器中。-Connection between ADC 0809, it was the eight CMOS A / D converters. Tablets containing eight analog switches, control eight of analog converters enter a Chinese.
Verilog_phone_countpay
- VerilogHDL编写的一个电话计费程序 具有一定的代表性-VerilogHDL prepared a telephone billing procedures for a certain degree of representativeness
FIFO.v
- 异步先进先出FIFO存储器，采用格雷码判定，消耗资源更小-Asynchronous FIFO FIFO memory, using Gray code determination, consume less resources
sram
- sram 读写小程序，用verilog编写的，请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
BCD_adder
- VHDL code for a one bit comparator and an n bit register and a BCD adder
del_ctrl_rtl
- A VHDL logical example of memory delay controller -A VHDL logical example of memory delay controller
digital_clock
- 数字钟vhdl程序，能够显示年月日，时分秒，还有闰年-digital_clock.It can show the year,month,day and so on.
AGC
- 在实际系统中，由于发端功率和信道增益的变化会引起接收到的信号幅度的变化，这种变化是设计者所不希望的，因此，有必要对信号幅度进行自动增益控制(AGC)。另外，在解调器内部所有同步完成之后，如果解调输出为软输出，则需要对输出信号进行定标，以使较少的位数能够全面地反映解调数据的信息，这被称为定标AGC。AGC的实现原理大同小异，一般都是将信号幅度(能量)与固定门限比较，高于或低于门限的信息被送到调整环路滤波器，滤波器的输出用于控制可控增益放大器，或者是数字增益调整。-AGC
time_cnt
- very good programme for you
convol_enc
- VHDL code for convolution encoder for wimax PHY layer. This design also has control to add controlled amount of noise in encoded output.