资源列表
rs232_receive_control
- RS232 receive control in VHDL
counter60
- this a counter. it can count from 0 to 50-this is a counter. it can count from 0 to 50
fan_control
- Verilog 语言下的风扇转速监控以及风扇转速PWM控制-Verilog language,fan speed monitor and fan speed control by PWM
keyscan66
- 6*8VHDL按键扫描，供大家学习参考。-6* 8VHDL button to scan for the reference U.S. study.
RTC_Test_Top
- 用Actel公司的Fusion系列FPGA开发的RTC实验程序-With Actel' s Fusion Series FPGA development of experimental procedures RTC
spimaster
- spi总线在fpga上的实现，用verilog语言编写，可用，实际操作过-spi bus implementation on fpga, verilog language use, available over the actual operation
Floor
- 多层电梯的控制系统 控制电梯根据内外按键上下停-Multi-elevator control system control buttons up and down the elevator to stop internal and external
vg
- 通过vhdl编程实现利用vga显示横向、纵向的彩条码。和棋盘形码-By vhdl programming the vga display horizontal and vertical color bar code. And board barcode
serialtoparellel
- 很好的串口转换程序，很好用。都试过，跑过很多遍，而且已经应用在产品设计中-Serial conversion process very good, very good. Tried everything, ran many times, but has been applied in product design
spislave1
- SPI slave communication
HalfbandDec
- 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
testHDLADJ64M
- 64k 帧头的猫述与实现，以及帧的误判以及相关的处理办法-64k header cat references and implementation, as well as false positives and the associated frame approach