资源列表
dcf089f8-85a5-44b9-98d9-e667ba564784
- 除法器能够做除法运算能够做除法运算 除法器能够做除法运算能够做除法运算-Divider can do can do division division
fsm_moore_3_always
- 使用3個always (三段式)來實現Moore FSM。 -Moore FSM
startstopwatch
- 利用VHDL编写的电子计时计分表，该程序简单，易懂-Written using VHDL electronic timing scoring table, the program is simple, easy to understand
cordic
- cordic 算法的FPGA实现，在Altera公司CycloneIII系列EP3C240C8Q芯片上验证通过-the inplemention of cordic algorithm in FPGA
ADC_TLC549
- ADC549的驱动，非常详细的解释和描述-drive for ADC549
divider
- 用VHDL编写的多次分频器，带有VHDL测试平台代码-Multiple frequency divider with VHDL testbench code
c21_pn_code_generator
- 精通verilog HDL语言编程源码之7——伪随机序列应用设计-Proficient in programming language source verilog HDL of 7- the application of pseudo-random sequence design
shiftregister
- Shift Register. VHDL code and its testbench.
ad_da_test
- 基于SOPC EP2C5开发板的I2C总线的A/D D/A例程-A/D AND D/A routings interfaced with i2c based on sopc ep2c5
ps2
- FPGA实现ps2键盘控制，sparden 3s 250e-FPGA realization of ps2 keyboard, sparden 3s 250e
bis
- 这是个并串转换的程序，用vhdl编写，希望对大家有用。-This is a string and the conversion process, using vhdl write, want to be useful.
DIV
- 最新修改 veilog 除法器，32位除16位，输出数据锁存-//divider dividend divisor* quotient+ remainder //dividend 32 bit //divisor 16 bit //quotient 32 bit //remainder 32 bit //need 32 clk to finish the calculation //start 1 start the calculation //s