资源列表
atan_lut
- atan LUT in VHDL program
vhdl2
- VHDL语言程序 用于偶数分频器 偶数值可修改-VHDL language program for the even-divider values can be modified even
miaobiao
- 实验课编写的vhdl程序，秒表适用！具体功能是开始计时，停止，清零！经实验，完美运行！-Vhdl program written by the Lab, stopwatch applicable! Specific start time, stop, clear! The experiment, a perfect run!
HDB3
- 用VerilogHDL实现了从NRZ码到HDB3码的编码过程-NRZ code to HDB3 code using VerilogHDL
Adder
- 8bit low power pipelined adder-8bit low power pipelined adder
RegGroup
- 这是32位的寄存器组，是用verilog编写的，包括源地址及目的地址的选择-This is a 32-bit register group, is prepared verilog, including the source address and destination address selection
float
- 基于Verilog HDL的32位浮点运算加法器的源代码。-Based on the 32-bit floating point adder in Verilog HDL source code.
Ch3
- 《Verilog HDL数字系统设计及仿真》第三章源代码-Verilog HDL
gps_jiance
- 合并单元内GPS同步时钟的检测 合并单元内GPS同步时钟的检测
DC0809.vhd
- ADC0809 VHDL控制程序,基于VHDL语言，实现对ADC0809控制.-ADC0809 VHDL control procedures, based on the VHDL language, to achieve control of ADC0809.
SRAM
- FPGA控制SRAM的VERILOG源码-The VERILOG source code control SRAM FPGA
i2c_fsm.v
- This a verilog module which describes a i2c slave fsm with one-hot encode.-This is a verilog module which describes a i2c slave fsm with one-hot encode.