资源列表
alu_testbench_vhdl_689102300
- ALU的testbench测试，可联合仿真使用-The ALU testbench test can be co-simulation using
Omnivision SCCB interface verilog model
- Omnivision SCCB interface verilog model
verilog
- 数字锁相环电路verilog源代码 开发环境quartus-Digital PLL circuit verilog source code
fsm_moore_2_always
- 使用2個always去描述有限状态机的3個block，state register與next state logic合一 -state register and next state logic
paobiao
- 数字跑表，包含百分秒、秒、分，能在FPGA上下载并显示-Digital stopwatch, including hundredths of a second, seconds, minutes, can be downloaded and displayed on the FPGA
syn_FIFO
- 同步FIFO，主要用于数据缓存，给异步FIFO打下基础，是个不错学习例子，在ncverilog中仿真通过-Synchronous FIFO, mainly used for the data cache, and lay the foundation to the asynchronous FIFO, is a good example of learning through simulation in ncverilog
jiaotongdeng
- 理想状态的四路交通灯设计，用CPLD/FPGA驱动的，时间可以更改。-Ideal state of four traffic lights design, CPLD/FPGA-driven, time can be changed.
13
- FPGA工程师成长手册源码，可以帮初学者很好的学习掌握FPGA的开发应用。-FPGA S
wave_gen
- 波形发生器，带TESTBENCH， 多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH.
c19_CICfilter
- 精通verilog HDL语言编程源码之5--CIC积分梳状滤波器设计-Proficient in verilog HDL source language programming of 5- CIC Integrator Comb Filter Design
VHDLcode_registr
- VHDL implementation of registors
ami_encoder
- This a vhdl code for Alternate Mark inversion line coding, it is used for baseband transmission.-This is a vhdl code for Alternate Mark inversion line coding, it is used for baseband transmission.