资源列表
divider
- 位数可以任意修改的除法器，本人亲自测试，可以使用，效率和使用资源都是很少的-its a very good divider based on Verilog HDL
FR
- 基于FPGA的数字频率计的设计，可测量从1hz到10000hz，误差在1hz以内，是EDA课程学习很好的实例。
AD
- 基于ADC0809的数据采集系统，对0~5V电压采集，显示到数码管显示-ADC0809 based data acquisition system, for 0 ~ 5V voltage of the collection, display to the digital tube display
spi_interface
- coorunnerii spi interface master 中的spi与从设备的接口程序-coorunnerii spi interface master
RGB2YCbCr
- 图像转换的verilog代码（RGB图像转换为YUV图像）-The image conversion Verilog code (RGB image is converted to YUV image)
mimasuo
- 数码管的vhdl源程序，主要用在CPLD或者FPGA上。-it is vhdl language.
FND_TEST
- Hi, This Verilog practice code-Hi, This is Verilog practice code
verilog
- Verilog桶形移位寄存器，实现不溢出移位-Verilog barrel shift register, the shift towards non-overflow
K163_addition
- elliptic curve in GF2m
my_FIFO
- FIFO的verilog实现，成功通过验证，很好用需要的可以下载-Verilog implementation of FIFO successfully validated, the good need can be downloaded
bk
- 16位Brent-Kung加法器的verilog代码-the verilog code of the 16 bits of the Brent-Kung s adder
vhdlcodes
- its VHDL coding for full adder and full substractor. 1.Structural model for Half Adder 2.Structural model for Full Adder 3.VHDL code for BEHAVIORAL model of Full Adder 4.VHDL CODE: full substractor (dataflow): 5.VHDL Code:full substracto